A driver circuit for a line boosts signals transmitted over the line, which helps ensure that the signal reaches its destination. Such a driver circuit may be a driver circuit for a data communication pathway for data communication between functional units, such as e.g. a bus, a driver circuit for a data line inside a memory, or any other driver circuit for driving a line terminated by a load.
Minimising energy consumption related to data storage and transfer in data-dominated systems is critical for the design of embedded systems. Distributed memory organisations have been proposed as an efficient storage architecture alternative. However, the impact of interconnect overhead in these has traditionally been neglected, which is not acceptable anymore for deep sub-micron technologies.
Trends in miniaturisation and autonomy in future technologies (e.g. bio- and nano-technology) will increase the need for ultra-low power (ULP) systems on chip (SoC) while ensuring reliability of their operation. The most energy/delay critical components in modern SoCs are embedded memories, both for data and instruction/configuration storage. Usually, they use a distributed memory organization consisting of small size SRAM based caches and/or scratch-pad memories for bandwidth and power efficiency. This is especially true for the memories in the first layers of the memory hierarchy (close to the central processor) in low power SoCs.
Currently, state-of-the-art SRAM libraries offer a limited range of energy/delay trade-offs. However, a wider range is important to achieve ULP operation because this range can be exploited during system level exploration to significantly reduce overall system energy.
On the other hand these small size SRAMs become very sensitive to process variability impact due to the higher tolerances of the manufacturing process in the nanometer technology nodes. Indeed, the increasing difficulty in controlling the uniformity of critical process parameters (e.g. doping levels) in the smaller devices makes the electrical properties of such scaled devices much less predictable than in the past. Due to this, the sensitivity of the SRAM circuits, especially the memory cell stability (e.g. signal to noise margin) and the design rules to compensate for this, have gained most attention in industry.
The introduction of design margins to guarantee that the memory still works under all possible conditions is one of the most popular design techniques to guarantee functional and parametric yield. However, as technology scales down the impact of variability increases, hence also the required margin increases, as discussed by R. Heald in “Managing variability in SRAM designs”, ISSCC uProcessor Forum, 2004. This overhead becomes prohibitive in the nanometer era and some researchers start proposing run-time monitoring approaches, which characterize the real situation in space and time (see Austin T., Blaauw D., Mudge T., Flautner K. in “Making typical silicon matter with Razor”, IEEE Computer, Volume 37, Issue 3, March 2004, pp. 57-65; Nose K., Hirabayashi M., Kawaguchi H., Seongsoo Lee and Sakurai T., “Vth-hopping scheme to reduce subthreshold leakage for low-power processors”, IEEE journal of Solid-State Circuits, Volume 37, Issue 3, March 2002, pp. 413-419) and “configure” the module so as to compensate the effects of variability. This requires the introduction of configuration “knobs” in the critical modules to tune the run-time operation of the component when the default configuration mode does not meet the application timing constraints. When, for instance, due to the impact of process variability the default configuration is too slow, a faster configuration (e.g. a lower threshold voltage Vt or higher supply voltage Vdd) can be selected instead.
“Knobs” for functional blocks have been proposed for trade-offs using either supply voltage (Vdd) control techniques, as described by L. Benini and G. De Micheli in “System-level power optimization techniques and tools”, ACM Trans. on Design Automation for Embedded Systems (TODAES), Vol. 5, No. 2, pp. 115-192, April 2000, and/or back-gate biasing control (Vt tuning), as described by Nose K., Hirabayashi M., Kawaguchi H., Seongsoo L. and Sakurai T. in “Vth-hopping scheme to reduce subthreshold leakage for low-power processors”, IEEE Journal of Solid-State Circuits, Volume 37, Issue 3, March 2002, Pages 413-419, thus allowing dynamic and/or standby energy versus execution time trade-offs. However, as technology scales down the margin available for Vdd and Vt tuning clearly starts decreasing, thus leaving very little margin for delay compensation.
Clearly, these margins are insufficient for compensating process variability impact on delay. This is especially true for SRAMs where delay can drift as much as 40% with most of the samples becoming slower. Hence larger ranges are needed and it is believed by the present inventors that due to the difficulty of controlling the technology process these cannot be provided solely by technology parameter tuning.